1. Field of the Invention
The present invention relates to a lateral transistor and a method of making the same, and more particularly, to a lateral transistor used in a bipolar semiconductor integrated circuit device suitable for a high-speed logic operation circuit or an analog operation circuit in a high frequency region.
2. Description of the Prior Art
With development of fine pattern technology, an integration density of a bipolar semiconductor integrated circuit has been increased, and its parasitic elements have decreased to provide a high-speed operation.
In order to reduce dimensions of base and emitter regions to eliminate a capacitance between base and collector regions and unwanted parasitic components such as a base resistance, a transistor for bipolar semiconductor circuits having a structure shown in FIGS. 3 and 4 has been proposed.
FIG. 3 shows a bipolar transistor having an isolation layer of an oxide film. An N.sup.+ -type buried region 31 is selectively formed in a P.sup.- -type semiconductor substrate 30, and an N.sup.- -type epitaxial layer 32 is grown on the substrate surface. After an oxide film (not shown) is formed on the surface of the epitaxial layer 32, a P.sup.+ -type channel stopper 33 is provided at a predetermined position. Using LOCOS (Local Oxidation of Silicon) techniques, a field oxide film 34 is provided to surround the N.sup.+ -type buried region 31 formed in the P.sup.- -type semiconductor 30, and a region isolation oxide film is formed in the N.sup.+ -type buried region 31 through the N.sup.- -type epitaxial layer 32. Thereafter, a bipolar transistor having a P-type base region 35 and an N.sup.+ -type emitter region 36 is provided in one epitaxial layer 32 serving as a collector region, and an N.sup.+ -type collector contact layer is formed in the other epitaxial layer.
FIG. 4 shows a bipolar transistor having a trench isolation layer. After an N.sup.+ -type buried region 41 is formed in a P.sup.- -type semiconductor substrate 40, an N.sup.- -type epitaxial layer 42 is grown on the surface of the P.sup.- -type semiconductor substrate 40. A trench 44 is provided by means of RIE (Reactive Ion Etching) techniques so as to reach the semiconductor substrate 40 through the epitaxial layer 42 and the buried region 41. A P-type impurity is introduced into the bottom of the semiconductor substrate 40 exposed by the trench 44 so as to form a P.sup.+ -type channel stopper 43 having a high impurity concentration, and the trench 44 is filled with a desired insulator 46 through an oxide film 45. After a field oxide film 47 is formed on the substrate surface by known techniques, a doped polysilicon layer 48 serving as a base contact layer is deposited on the substrate surface. P-type impurity is then diffused in the epitaxial layer 42 to provide a P-type base region 49. The semiconductor substrate is subjected to an oxidation treatment to form an oxide film 51 thereon. Openings are then formed in the oxide film 51. An N.sup.+ -type emitter region 50 and an N.sup.+ -type collector contact layer 52 are formed in the P-type base region 49 and the N.sup.- -type epitaxial layer 42, respectively, by impurity diffusion from a doped polysilicon layer 53 deposited on the oxide film 51. Thereafter, an emitter electrode 54, a base electrode 55, and a collector electrode 56 are provided on the corresponding polysilicon layers to complete a bipolar transistor.
In the bipolar transistor having the structure shown in FIGS. 3 and 4, it is possible to decrease the dimensions or size of the field oxide isolation region and base and emitter regions. However, since the collector structure employs the thickness direction of the semiconductor substrate which includes the low impurity concentration region, the buried region and the contact region, it is difficult to reduce the dimensions thereof. In addition, it is difficult to decrease the collector series resistance and the parasitic capacitance between the collector region and the semiconductor substrate.